As geometries continue to shrink, silicidation of the gate, source and drain regions becomes more challenging due to the density and higher aspect ratios of transistor gate stacks. Excellent step coverage and thin film uniformity must be achieved on smaller, higher aspect-ratio features. In addition, the silicide material must provide low resistivity and gate leakage.

For 65nm/55nm and below Logic/Memory applications, silicon consumption by Co and roughness of the Co silicide/silicon interface become more critical. Applied Materials offers the Endura ALPS (Advanced Low-Pressure Source) Ni PVD system for stable NiSi films with 2x less silicon consumption, smoother film interfaces, and reduced resistivity. In addition, ALPS Ni provides superior bottom coverage with 100Å film and no plasma damage to the device while maintaining outstanding particle performance.

Siconi Preclean
The Applied Endura ALPS Ni PVD system features the single-chamber Siconi Preclean which provides breakthrough interface engineering technology to address the surface preparation challenges of cleaning silicon prior to the formation of NiSi. Siconi Preclean provides a highly selective clean (>20:1 SiO₂:Si, >5:1 SiO₂:SiN) without the need for the tight queue time control between clean and Ni deposition required with conventional HF clean processes. By generating the etchant in a remote plasma source, damage to the substrate is significantly reduced, resulting in minimal etching of features such as nitride spacers and the silicon gate. In addition, device studies show a reduction in NiSi₂ spike defects and improvement in junction leakage with the Siconi Preclean compared to conventional HF dip process flows.